Method for patterning mo layer in a photovoltaic device comprising cigs material using an etch process

ABSTRACT

A processing method described herein provides a method of patterning a MoSe 2  and/or Mo material, for example a layer of such material(s) in a thin-film structure. According to one aspect, the invention relates to etch solutions that can effectively etch through Mo and/or MoSe 2 . According to another aspect, the invention relates to etching such materials when such materials are processed with other materials in a thin film photovoltaic device. According to other aspects, the invention includes a process of etching Mo and/or MoSe 2  with selectivity to a layer of CIGS material in an overall process flow. According to still further aspects, the invention relates to Mo and/or MoSe 2  etch solutions that are useful in an overall photolithographic process for forming a photovoltaic cell and/or interconnects and test structures in a photovoltaic device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/562,573, filed Jan. 22, 2006 which is incorporated herein.

FIELD OF THE INVENTION Background of the Invention

Thin layers of material comprising Cu(In,Ga)Se, i.e. CIGS, are known toexhibit the highest photovoltaic conversion efficiency of any thin filmmaterial for a photovoltaic device (19.5%). See K. Ramanathan et al.,“Properties of High-Efficiency CIGS Thin-Film Solar Cells,” 31^(st) IEEEPhotovoltaics Specialists Conference and Exhibition, Lake Buena Vista,Fla., Jan. 3-7, 2005; and D. E. Tarrant et al., “CIS thin filmdevelopment and product status at Shell Solar, May 2003,” Proc. of3^(rd) WCPEC, Osaka, Japan, May 2003. Similar progress has been reportedin the manufacturing area, where the efficiency of champion modules hasexceeded 13% with yield above 80%. See M. Contreras et al., “HighEfficiency Cu(In,Ga)Se₂-Based Solar Cells: Processing of Novel AbsorberStructures,” Proc. of 1^(st) WCPEC, Hawaii, Dec. 5-9, 1994.Consequently, CIGS is considered by many in the art to be an attractivematerial for use in the manufacture of thin film photovoltaic panels.

In a typical solar cell module, as shown in FIG. 1A, a CIGS layer 106 isgrown to a thickness of about 2 μm on an underlying metal layer 104comprised of molybdenum (Mo). Mo provides good ohmic contact and has asimilar thermal coefficient of expansion as CIGS, which can be importantfor the elevated temperature of CIGS processing. The Mo is usuallydeposited on a substrate material 102 which may be, for example, glass,stainless steel, or plastic. A range of concentrations of Cu, In, Ga andSe can be used in the CIGS layer, and sometimes the Ga is absent or Smay be added. Accordingly, CIGS is used herein in its broadest possiblemeaning in the context of similar or related films. Moreover, othermaterials may be used in thin film photovoltaic modules, eitherindividually or in combination, and either alternatively oradditionally. These include CdTe, amorphous silicon (a:Si) and micro- ornano-crystal silicon (μc:Si). See generally, Y. Hamakawa (ed.),“Thin-Film Solar Cells,” Chapter 10 (2004), the contents of which areincorporated herein by reference.

While the above-mentioned reported efficiencies of thin-filmphotovoltaic modules including CIGS are promising, there is a large gapbetween those numbers and actually-obtained efficiencies of knowncommercial photovoltaic modules containing CIGS. One problem is thatlaser and mechanical scribes are commonly used to pattern and forminterconnects in thin-film photovoltaic modules, and these prior artprocesses have a number of drawbacks that limit module efficiency. Forexample, they create wide scribes, defects, and shunt current paths.Furthermore, they provide limited means for wiring the module inseries-parallel arrangements that might reduce sensitivity to seriesresistance, shading losses or non-uniformity.

For these and other reasons, some have considered using lithographicpatterning processes to form thin-film photovoltaic moduleinterconnects. However, these processes would require the ability toetch Mo, and, in some cases, to do so selectively so that, for example,the etch will not induce excessive undercut of an overlying CIGS layer.The prior art literature provides scant reference to etching Mo in aCIGS solar cell, and is otherwise insufficient to solve this problem.

Moreover, it was not even known to etch CIGS in a solar cell until theinvention of U.S. patent application Ser. No. 11/395,080 (AMAT-10936),the contents of which are incorporated herein by reference. While thisinvention dramatically advanced the state of the art of thin-filmphotovoltaic modules, and also mentions etching Mo, additional problemshave arisen that were not seriously addressed before that invention.

For example, as shown in FIG. 1B, certain CIGS growing processes caninclude selenium annealing at high temperature. In such processing, aMoSe₂ layer 108 is formed at the interface between the CIGS layer 106and Mo layer 104.

When such a MoSe₂ layer is formed, both the Mo layer and this additionalMoSe₂ layer need to be removed during processing, and ideally using anetch. Again, the prior art literature is insufficient for overcomingthis newly-observed problem. For example, T. Ohmori et al., in theirarticle entitled “pH Dependent Controlled patterning of p-MoSe₂ Surfacesby In-Situ Electrochemical Scanning Tunneling Microscopy,” Langmuir, 14(21), 6287-6290 (1998) propose using a solution of 0.05M NH₃ and 0.025MKNO₃ with the assistance of a high electrical field induced between anAtomic Force Microscope (AFM) tip and a MoSe₂ surface. For a typical gapof 2 nm between the AFM tip and the substrate and with the reportedetching threshold voltage of 0.3V, the electrical field is as high as1.5×10⁸ V/m which is unsuitable for application to macro-scale processessuch as photovoltaic module fabrication. Likewise, S. Chandra and S. N.Sahu, in their paper entitled “Electrodeposited semiconductingmolybdenum selenide films: I. Preparatory technique and structuralcharacterization,” J. Phys. D: App. Phys., Vol. 17 (1984), pp.2115-2123, propose an electro-deposition method of MoSe₂ films. Whilethe article implies a MoSe₂ etch in basic solutions, no etch recipe isgiven, and in any event it does not describe a useful process forphotovoltaic module fabrication.

Therefore, there remains a need in the art to overcome many of theshortcomings of the conventional processes for etching an underlyingmetal Mo layer in a thin-film photovoltaic device having CIGS material.The present invention aims at doing this, among other things.

SUMMARY OF THE INVENTION

The present invention provides a method of patterning a MoSe₂ and/or Momaterial, for example a layer of such material(s) in a thin-filmstructure. According to one aspect, the invention relates to etchsolutions that can effectively etch through Mo and/or MoSe₂. Accordingto another aspect, the invention relates to etching such materials whensuch materials are processed with other materials in a thin filmphotovoltaic device. According to other aspects, the invention includesa process of etching Mo and/or MoSe₂ with selectivity to a layer of CIGSmaterial in an overall process flow. According to still further aspects,the invention relates to Mo and/or MoSe₂ etch solutions that are usefulin an overall photolithographic process for forming a photovoltaic celland/or interconnects and test structures in a photovoltaic device.

In furtherance of these and other objects, a method of processing athin-film structure according to the invention includes etching a thinfilm layer in the thin-film structure, wherein the thin film layercomprises molybdenum. In certain embodiments, the etched thin film layerfurther comprises selenium. In other embodiments, the etched thin filmlayer comprises Mo and MoSe₂. In additional embodiments, the methodfurther includes defining a masking layer so as to pattern the thin filmlayer. In other embodiments, the thin-film structure includes aphotovoltaic film such as CIGS.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and features of the present invention willbecome apparent to those ordinarily skilled in the art upon review ofthe following description of specific embodiments of the invention inconjunction with the accompanying figures, wherein:

FIGS. 1A and 1B illustrate certain aspects of the processing ofthin-film structures including CIGS and an underlying conductor;

FIGS. 2A and 2B illustrate an example process of etching a Mo/MoSe₂material in accordance with one embodiment of the invention; and

FIGS. 3A-I show a method of forming a thin film photovoltaic moduleincluding an underlying Mo/MoSe₂ conductor using a photolithographicetch process in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described in detail with reference tothe drawings, which are provided as illustrative examples of theinvention so as to enable those skilled in the art to practice theinvention. Notably, the figures and examples below are not meant tolimit the scope of the present invention to a single embodiment, butother embodiments are possible by way of interchange of some or all ofthe described or illustrated elements. Moreover, where certain elementsof the present invention can be partially or fully implemented usingknown components, only those portions of such known components that arenecessary for an understanding of the present invention will bedescribed, and detailed descriptions of other portions of such knowncomponents will be omitted so as not to obscure the invention. In thepresent specification, an embodiment showing a singular component shouldnot be considered limiting; rather, the invention is intended toencompass other embodiments including a plurality of the same component,and vice-versa, unless explicitly stated otherwise herein. Moreover,applicants do not intend for any term in the specification or claims tobe ascribed an uncommon or special meaning unless explicitly set forthas such. Further, the present invention encompasses present and futureknown equivalents to the known components referred to herein by way ofillustration.

Generally, the present inventors have discovered several etch solutionsthat can effectively etch through Mo and/or MoSe₂, and particularly whensuch materials are patterned during photolithographic processing withother materials such as CIGS in a thin film photovoltaic device.

FIGS. 2A and 2B illustrate a first example embodiment for patterning Moand/or MoSe₂ in accordance with the invention. In this example, an etchsystem comprising a 1:1 combination of H₂O₂ and NH₄(OH) is prepared foruse. It should be noted that the below described drawings are not toscale, and relative dimensions of various layers and features will bespecified in the descriptions where examples are appropriate. Thedrawings are intended for illumination rather than limitation.

As shown in FIG. 2A, a thin-film Mo and/or MoSe₂ layer 204 is preparedon a substrate 202 using any one of a known number of thin-filmtechniques such as sputtering, evaporation, chemical vapor deposition orplating, for example. It should be noted that one or more thin-filmlayers of other materials may be included, above and/or below the Molayer 204 with respect to the underlying substrate. A mask 206 issuspended on or over the substrate, the mask including an aperture 208representing a portion of a desired pattern. The above-describedH₂O₂/NH₄(OH) etch system is used to etch the thin-film structure throughthe aperture. Other etch systems may be needed to etch through otherlayers if they exist in this structure. For example, a staged etchprocess may be used.

As shown in FIG. 2B, the etch system above completely etches thestructure corresponding to the mask aperture 208 through the Mo layer204 and possibly down to the substrate 202. The mask can then be removedand/or the same or other masks used to further process the thin-filmstructure.

While the etch system of this embodiment of the invention completely andsuccessfully etches Mo and MoSe₂, its etch selectivity between MoSe₂/Moand certain masks such as certain types of photoresist is low, and sosuch masks or photoresists may be heavily damaged using this etchsolution. Accordingly, the mask may not be usable for subsequentprocessing and may need to be removed after the etch. Accordingly, theusefulness of this etch system may be limited in patterning applicationssuch as photolithographic processing.

Moreover, when one of the layers other than Mo/MoSe₂ in the thin-filmstructure is a CIGS layer, the exposed CIGS film will induce intensereaction of CIGS and H₂O₂, which causes the process to become very hardto control and can result in severe undercut of the CIGS film.

Another preferred embodiment of the invention is shown in FIGS. 3A-3F.This embodiment is illustrated in connection with an example processflow of forming a CIGS thin film solar cell. While the etch process ofthis embodiment provides many advantages in such a process flow, theinvention is not limited to this particular application.

The process starts as shown in FIG. 3A, where a starting materialcomprising stack 300 is formed on a substrate 312 such as a 3 mm thicksheet of soda lime glass (SLG). As shown, stack 300 includes a 1 μmlayer 302 of Mo, corresponding to the opaque metal electrode in contactwith the glass substrate 312, a 2 μm CIGS semiconducting or absorbinglayer 304, under a 0.07 μm buffer layer 306 of CdS. While the use ofCIGS is illustrative of certain aspects of this embodiment, any otherappropriate semiconducting or absorbing material including micromorph,CIS, α:Si, μC:Si, CdTe, or stacks of multiple materials, could also beused, and the buffer layer need not be included.

It should be noted that before CIGS material deposition, in someembodiments a thin compound layer containing Se is first deposited ontop of the Mo film to act as a seeding layer for CIGS growth. In thisexample process, Se atoms diffuse into Mo and can form a MoSe2 layer(not shown) at the interface between CIGS layer 304 and the Mo layer302.

The next step in the process flow is to make an isolation cut throughthe stack 300 to the glass. According to an aspect of this embodiment ofthe invention, photolithographic processing is used. For example, inthis embodiment shown in FIG. 3B, a layer 314 of photoresist is appliedto the module, for example by spinning a layer of Shipley 3612photoresist on the sample. The thickness of the photoresist may be 1-10μm. Lines 316, for example 10 μm wide, are exposed in the photoresistusing, for example, a photolithographic mask (not shown) with acorresponding aperture suspended above or in contact with the substrate.

In this example application of forming a photovoltaic module, theselines 316 are used to divide the module into cells and can run theentire length of the module. These lines are also used in the process offorming interconnects between cells as will be described in more detailbelow. It should be noted that in this step, many hundreds of theselines substantially parallel to each other can be formed on the module.Moreover, other lines and patterns may be made during this step, forexample corresponding to test structures and lines for parallel wiringarrangements. Discussions of such other alternative or additionalprocessing will be omitted here for the sake of clarity of theinvention.

As shown in FIG. 3C, after hard bake of the photoresist, a staged etchprocess is used to form the isolation cut. First, the CIGS film 304 isetched with, for example, a mixture of 98% concentration H₂S0₄ and 30%concentration H₂O₂ at the ratio of 5:1 at 40 C and/or other techniquesas described in co-pending application Ser. No. 11/395,080 (AMAT-10936).

According to an aspect of the invention, the same photoresist mask canalso be used as an etch mask for a subsequent wet etch of the MoSe₂/Molayer 302. For the MoSe₂/Mo etch, the present inventors have discoveredthat a strong oxidizer solution of NaClO, for example as that solutionis found in bleach such as Clorox® bleach, is able to remove the Molayer as well as the thin MoSe₂ layer that is present in the CIGS solarcells of certain embodiments. The etch rate is about 10 {acute over(Å)}/sec and takes less than 2 minutes to cleanly remove MoSe₂/Mo filmshaving a thickness of approximately 1 μm.

In general it is desirable to have at least 5:1 etch rate selectivitybetween MoSe₂/Mo and both CIGS and the photoresist, in order to have awide enough process window to minimize the undercut of CIGS. It is foundthat this selectivity is obtained for Mo and Shipley 3612 photoresistwith the above described NaClO solution (i.e. Clorox® bleach).Therefore, it is possible to perform an etch using this etch system andusing a photoresist mask for patterning the Mo layer.

FIG. 3D illustrates a next step which begins a process of forming aconductive step or contact step according to one preferred embodiment offorming a photovoltaic device. As shown in FIG. 3D, this includesdepositing another layer of photoresist 314′, which can be the sameShipley 3612 photoresist as photoresist layer 314, and the applicationprocess can be a spin-on process as described above. Next, a secondaperture 316′ that is aligned with one side of the first narroweraperture 316 is patterned in the photoresist.

For example, in accordance with techniques described in more detail inco-pending application Ser. No. 11/394,721 (AMAT-10668), the contents ofwhich are incorporated herein by reference, a reflector or mirror isplaced in close proximity to the top surface (e.g. 50 μm) and theillumination is incident from the under side of the glass substrate 312at an angle. The light reflects from the mirror and exposes a region ofphotoresist adjacent to the already formed scribe 318. Therefore, thisexposure is self-aligned to the existing scribe, and creates a 30 μmwide aperture in the module having one edge corresponding to the line318.

As shown in FIG. 3E, following exposure, development and removal of thephotoresist region, an etch is performed through the exposed structureto form the conductive step 310 and interconnect groove 330. This etchmay be done using the mixture described above comprising 98%concentration H₂S0₄ and 30% concentration H₂O at the ratio of 5:1 at 40C, and/or other wet or dry etch techniques as described in co-pendingapplication Ser. No. 11/395,080 (AMAT-10936). In some embodiments, theetch is stopped when the Mo layer 302 is reached. In other cases, theetch may be stopped in the semiconductor layer. For example, in α:Si orμC:Si the semiconductor is heavily doped near the bottom, and contact tothis heavily doped region is acceptable. The heavily doped region can beleft with metal to form interconnects due to the region's good electricconductivity.

It should be noted that other wet etch solutions may be possible, aswell as dry etch processes. Although dry etches are commonly used inlithographic processing, they are generally more costly than wet etches.Dry etches usually involve chemical reactions using ions in a plasma tocreate volatile by-products. Moreover, the dry etch equipment may not beavailable for large substrate processes. An advantage of the wet etchprocess examples provided herein is that they include the use ofinexpensive chemicals such as sulphuric acid and peroxide. It is alsopossible to use plasma etching to remove these films, but the cost ofthe equipment would be much higher than wet etch processes.

In the next step shown in FIG. 3F, processing continues by applying aninsulator to the exposed edges or walls of the CIGS semiconductor layer304 adjacent to the interconnect groove 330 between cells. Morespecifically, in the embodiment shown in FIG. 3F, resist 314″ isdeposited and then patterned to expose the CIGS edges through openings316″. As should be apparent, an aligned lithographic process such asthat described in FIGS. 3B and 3D can be performed to pattern the resistand create openings 316″. In this example, however, a lift-off resistsuch as ProLift 100 from Brewer Science is preferably used, as willbecome more apparent from below. A thin insulator layer 320 such as SiO₂or Al₂O₃ is then sputtered to a thickness of 500 Å.

Removing the photoresist lifts off the insulator deposited thereon,leaving portions of insulator 320 on the opposing walls of the CIGSlayer adjacent to the interconnect groove 330 that were exposed throughopenings 316″, as shown in FIG. 3G.

A layer 322 of a transparent conductor such as 0.7 μm of aluminum dopedzinc oxide (AZO) is deposited over the surface of the stack 300 in anext step shown in FIG. 3H.

In a next step shown in FIG. 3I, the layer 322 is patterned (e.g. usinglithographic techniques as described in FIGS. 3B and 3D, for example),to form a series connection 324 between adjacent cells. As shown in FIG.3I, the insulator material 320 underlies the connection 324, thuseliminating the current shunt path formed between the connection 324 andthe portion of the CIGS layer 304 and the underlying Mo conductor 302abutting the sidewall edge of the cell.

It should be noted that, in addition to dividing cells and forminginterconnects, the etch and patterning processes described above can beused to form test structures, for example, adjacent to the active area,or even in a small portion of the active area. For example, the etchingcan be used to isolate a small portion of a deposited film, so thatproperties such as thickness or conductivity can be measured. In somecases, an earlier deposition may be etched away in an earlier processstep, so that a later deposition is formed on the glass substrate,allowing the later deposition to be electrically isolated, withunderlayers absent. This allows intermediate process parameters to bemeasured by probing before the full process is complete.

Moreover, as set forth in co-pending application Ser. No. 11/395,080(AMAT-10936), the CIGS etch and patterning process described above mayalso be used for other purposes. For example, the process can be used toform contact pads or to place small surface-mount protect diodes. Inaddition, it is possible to perform the process of edge isolation whileperforming the cell division using the CIGS etch process. Edge isolationis the process of removing deposited layers from the edges of themodule, so they will not run over the edge and short out. This processis normally done using laser scribing, but can be included in the celldivision etch process (e.g. as shown in FIGS. 3D and 3E) by adjustingthe mask to expose the periphery of the module. In addition, aninsulator such as insulator 320 can be formed over the edge isolation atno additional cost in order to passivate the exposed edge, thus reducingedge leakage and making the exposed edge impervious to contamination.

Although the present invention has been particularly described withreference to the preferred embodiments thereof, it should be readilyapparent to those of ordinary skill in the art that changes andmodifications in the form and details may be made without departing fromthe spirit and scope of the invention. It is intended that the appendedclaims encompass such changes and modifications.

1. A method of processing a thin-film structure comprising: etchingcompletely through a portion of a thin film layer in the thin-filmstructure, wherein the thin film layer comprises molybdenum, therebycompletely exposing a corresponding underlying portion of the thin-filmstructure that does not comprise molybdenum.
 2. A method according toclaim 1, wherein the etched thin film layer further comprises selenium.3. A method according to claim 1, wherein the etched thin film layercomprises Mo and MoSe₂.
 4. A method according to claim 1, furtherincluding defining a masking layer so as to pattern the thin film layerand thereby define the etched portion of the thin film layer.
 5. Amethod according to claim 1, wherein the etching step includes using awet etch chemistry.
 6. A method according to claim 1, wherein theetching step includes using a dry etch chemistry.
 7. A method accordingto claim 5, wherein the etched thin film layer comprises a conductingfilm in a solar cell stack.
 8. A method according to claim 5, whereinthe thin-film structure further comprises a different layer comprisingCIGS film.
 9. A method according to claim 5, wherein the thin-filmstructure further comprises a different layer comprising CdTe.
 10. Amethod according to claim 5, wherein the thin-film structure furthercomprises a different layer comprising amorphous silicon.
 11. A methodaccording to claim 5, wherein the thin-film structure further comprisesa different layer comprising micro- or nano-crystal silicon.
 12. Amethod according to claim 5, wherein the wet etch chemistry includesNaClO.
 13. A method according to claim 1, wherein an etch rate is inexcess of 5 Å/sec.
 14. A method according to claim 1, wherein thethin-film structure further comprises a photovoltaic film layer, andwherein an etch rate at which the etching removes the thin film layer isat least 5 times greater than an etch rate at which the etching removesthe photovoltaic film layer.
 15. A method according to claim 14, whereinthe photovoltaic film comprises CIGS.
 16. A method according to claim 4,wherein the step of defining the masking layer includes depositing aphotoresist layer and using photolithography to create a pattern, andwherein an etch rate at which the etching removes the thin film layer isat least 5 times greater than an etch rate at which the etching removesthe photoresist layer.
 17. A method according to claim 1, wherein theetching step further includes forming test structures in the thin filmstructure.
 18. A method according to claim 17, wherein intermediatelayers in the thin-film structure are removed so that the teststructures are formed on a base that includes fewer layers than theentire thin-film structure at the point in the process.
 19. A methodaccording to claim 17, wherein the test structures are electricallyisolated from an actual device formed in the thin-film structure.